Conventionally, as a circuit to receive a minimum shift keying signal and perform frequency correction processing, a reception processing circuit to facilitate demodulation processing and the frequency correction processing by converting an MSK signal to a binary phase shift keying (BPSK) signal is disclosed.
The conventional reception processing circuit converts a radio frequency signal modulated by a minimum shift keying scheme to a BPSK signal by performing frequency conversion by an IQ demodulator, performing AD conversion by an AD converter and detecting an amount of phase offset and an amount of frequency offset between a transmitter and a receiver by an ArcTan circuit.
Then, the reception processing circuit performs initial correction and tracking correction of the phase offset and the frequency offset between the transmitter and the receiver by synchronizing a numerically controlled oscillator (NCO) in a digital baseband with the detected frequency offset and subtracting an output phase of the NCO from phase data after demodulation.
In the frequency correction method by the conventional reception processing circuit, however, since frequency offset correction is performed with the use of an in-phase component and a quadrature component of a received signal, a quadrature demodulator, an analog filter for quadrature component, an AD converter for quadrature component, an ArcTan circuit for phase detection and the like are required. Thus, there is a problem that the circuit scale and power consumption are large.